The present invention relates generally to semiconductor device fabrication and, more particularly, to methods responding to an electrostatic discharge (ESD) event on a voltage rail, as well as ESD protection circuits and design structures for an ESD protection circuit.
Modern electronics achieve high levels of functionality in small form factors by integrating multiple functions onto a single chip. A common fabrication process that allows high levels of integration at a relatively low cost is complementary metal-oxide-semiconductor (CMOS). CMOS processes build a combination of p-type and n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) to implement logic gates and other types of digital circuits.
Chips may be exposed to ESD events leading to potentially large and damaging currents within the integrated circuit. Increasing integration densities and performance demands on CMOS chips have resulted in reduced device dimensions. The reduction in dimensions has increased the susceptibility of integrated circuits to ESD events. Manufacturers, assemblers, and users of integrated circuits must therefore take precautions to avoid unintentionally causing ESD events. For example, ESD prevention can be incorporated into the integrated circuit and may include special design techniques for input/output (I/O) pins and pads to prevent damage to the chip during handling from the time that the chip is manufactured until the time that the chip is installed on a circuit board.
Effective ESD protection for a power supply pad typically requires a circuit that provides a low impedance path to direct ESD currents away from the integrated circuit during the ESD event, but remains in a high impendence state when the integrated circuit is powered under non-ESD conditions. Circuits that include a clamp device, such as a semiconductor-controlled rectifier (SCR) or MOSFET are often used to provide this type of ESD protection in CMOS applications, but typically require a trigger circuit to function properly. The trigger circuit may include a resistor-capacitor (RC) circuit having a time constant sufficient to keep the clamp device triggered for the duration of an ESD event, but that prevents the clamp device from triggering undesirably during a normal power up sequence.
Therefore, improved methods responding to an electrostatic discharge (ESD) event on a voltage rail, as well as ESD protection circuits and design structures for an ESD protection circuit are needed.